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Governing the use of technical articles, source code implementations, hardware benchmarks, and interactive calculators on Global Tech Digest.

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Many articles on Global Tech Digest cover low-level hardware and kernel configurations—including NVIDIA Management Library (NVML) clock locking, GPU power capping, PCIe Access Control Services (ACS) BIOS modifications, Linux kernel eBPF socket redirection, and Kubernetes SR-IOV device plugins:

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Kernel Engineering Under Physical Non-Idealities: Floorsweeping, Wave-Equalized Launches, and the DVFS Confounder Behind H100 Clustering Gains

GPU SYSTEMS An NUS team shows the H100 you programmed is not the H100 you have: fabrication binning quietly removes whole SMs from cluster reach, and power limits rewrite the speedup math. Accounting for both recovers up to 5.30% on FlashAttention 4. By Ossam Hashim KEY FINDINGS Floorsweeping, the binning step that disables defective silicon to salvage a die, is invisible to the ISA but visible to cluster placement: on the H100 SXM5 it removes GPC-level clustered execution capacity, cutting SMs reachable by clusters from 132 to 124 (paper's measurement). Cluster placement also drifts at runtime: the paper's microbenchmark records only 120 unique SM IDs per kernel iteration but 124 across iterations, so the effective SM budget oscillates launch to launch. Fewer usable SMs can add a full execution wave: a launch that needs one wave at 132 SMs can need two at 120, erasing the data-movement savings DSMEM clustering was supposed to buy. The fix is arithmetic,...

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